The present invention relates to memory devices and, more particularly, to an electron-beam-addressed charge storage memory having an improved target for facilitating relatively greater numbers of erase/write operations.
Electron-beam-addressable memories utilizing a multi-layered memory target, particularly a target of the metal-oxide-semiconductor type, are well-known. One such target structure is disclosed and claimed in U.S. Pat. No. 3,761,895, entitled "Method and Apparatus for Storing and Reading Out Charge In an Insulating Layer", issued Sept. 25, 1973 and assigned to the assignee of the present invention. The target described in the aforementioned patent, incorporated herein by reference, allows binary data to be stored as a pattern of electrical charge written into the insulating oxide layer, by means of a modulated electron beam impingent thereon. The stored electrical charge patterns are read by scanning the electron beam across a desired area of the target to vary the current through a reverse-biased p-n junction underlying the oxide layer and in accordance with the presence or absence of a charge site in the latter. It has been found that memory target operation is somewhat degraded after the target receives an electron beam dose of a few coulombs per square centimeter, commensurate with a certain number of reading, writing and erasing operations. A target, of the metal-oxide-semiconductor type, which provides discernable differences in gain, during a reading operation, responsive to an area of the target having charge present or devoid thereat, even after electron beam dosages due to reading, writing and erasing in excess of 10 coulombs per square centimeter, is highly desirable.